SpectaReg is an Electronic System Level (ESL) development framework provided by PDTi that makes memory mapped registers (aka register-maps) really easy for chip development teams. SpectaReg provides a rich and intuitive user interface for specifying register-maps, and with a mouse click dependent design, testing and documentation deliverables are generated (Verilog, SystemVerilog, VHDL, C/C++, HTML, DocBook, DITA). Specifications are stored in the SPIRIT Consortium's IP-XACT XML standard and the framework is extensible using Python.


SpectaReg (last edited 2014-04-26 07:45:12 by DaleAthanasias)

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